1. Field of the Invention
The invention relates to an MOS transistor with high output voltage endurance.
2. Description of the Background Art
In a large number of applications, it is desirable that MOS transistors not be destroyed at their output even in case of high output voltages between 180 V and 200 V. It may happen that a circuit is briefly exposed to such high output voltages due to external influences. Such high voltage peaks occur especially in electronic circuits for motor vehicles. That region of an MOS transistor which is most susceptible for a (irreversible) breakdown is the drain-side edge of the gate because rather high electric fields will occur there due to the edge effect. Notably, for reaching a low switch-on resistance, it is desirable that the region between the drain-side edge of the gate and the drain connector itself has a good electric conductivity. This, however, means that the whole output voltage (in the switched-out condition of the transistor) will decrease in the region of the drain-side edge of the gate. Since the gate oxide layer must have a very small thickness, MOS transistors have only a low output voltage endurance unless special measures are taken.
EP-A-0 449 858 describes an NMOS transistor with increased output voltage endurance. In this transistor, the (excessively doped) drain connection area is surrounded by a less doped well of the same conduction type as in the drain connection area. (In case of an NMOS transistor, this conduction type is the n-type conduction.) This less doped n-type well extends to a region below the drain-side edge of the gate oxide layer. The n-type well is produced by ion implantation and subsequent outdiffusion. As a result of the weaker doping as compared to the drain connection area, a doping area with reduced surface concentration in the lateral direction will be generated between the drain connection area and the drain-side edge of the gate oxide layer. In this weaker-doped n-type well area, which is formed in a p-type substrate, a space-charge zone can then be generated to a sufficient extent to make the NMOS transistor resistant to breakdown even in case of higher output voltages. However, the measure described in EP-A-0 449 858 does not allow for any desired increase of the output voltage endurance of the MOS transistor, so that this approach has its limitations.